Impact of Transformations on Memory Accesses

This paper presents code transformations designed to take advantage of the potential 2 orders of magnitude bandwidth increase available in a PIM-based architecture. Using an image processing application as a case study, we demonstrate how code transformations can exploit: (1) fine-grain parallelism in the wide-word processing unit to maximize the computation performed on each processor cycle; (2) data reuse in the large register file to avoid unnecessary memory accesses that stall the processor; and, (3) page mode accesses in the memory array to minimize the cost of each remaining memory access. While most of the transformations described here are well-known compiler techniques, in PIM-based systems we require a new optimization strategy to meet a very different optimization goal as compared to conventional approaches focused primarily on exploiting locality in a data cache. We demonstrate the importance of each set of transformations through simulation results.